When integrated circuits are manufactured, there is typically a substantial probability that a particular chip will not function as designed. Because of minor manufacturing variabilities, a given chip may not provide the correct outputs for a particular set of inputs. Such faults often occur randomly from one chip to the next. Accordingly, standard practice is to subject each chip to a test pattern and then to measure the output. Pomeranz et al in U.S. Pat. No. 3,927,371 applies the test pattern to a physical circuit and also to a computer simulation of the circuit and compares the results. However, it is fairly common that a fault is manifested only for a particular test pattern. For relatively simple integrated circuits, such as flip-flops, it would be possible to provide a series of test patterns that would test all possible combinations of input patterns. Thus, such a simple chip would be completely tested. However, advanced integrated circuits may use a very large number of input variables. This is particularly true when the integrated circuit includes memory elements so that the inputs of one cycle are tested only in subsequent cycles. Although it may be theoretically possible to completely test all input patterns, even the fastest automated testers would not be able to complete the testing in a reasonable time, more or less, at a low cost. Accordingly, it is desirable that during the design of an integrating circuit, a sequence of test patterns are generated which will catch all possible faults in the circuit. The number of test patterns should be reduced to as low a number as possible in order to reduce the testing costs. This type of fault simulation to determine testability is described by Chao et al. in U.S. Pat. No. 3,775,598. The generation of these test patterns requires a knowledge of the design of the circuitry as well as a knowledge of the likely faults that will occur in the circuit.
Fault simulation requires a workable model of the integrated circuit and possible faults are then inserted into the model, corresponding to possible faults in the real chip. Then a test pattern is generated which would catch that particular fault, that is, the test pattern generates one output with the faultless model and another output when the model includes the fault. This pattern is used in the testing of the actual integrated circuit to determine if the circuit is faulty. Obtaining the required test pattern is non-trivial because many faults will provide correct outputs for a large fraction of input patterns. Goel in U.S. Pat. No. 4,204,633 discloses a method of generating a test pattern that makes an inserted fault visible at the outputs. Needless to say, a substantial number of test patterns may still be required to catch all or substantially all faults. But the intelligent choice of test patterns substantially reduces the costs of testing or, alternatively, increases the coverage (i.e. the percentage of detected faults) for a given number of test patterns.
There are various levels of abstraction for the circuit model that can be used in the fault simulation. A general description of simulators of different levels is contained in a technical article entitled "A System Engineer's Guide to Simulators" by Werner et al appearing in VLSI Design, February 1984, pp. 27-31. One type is described by Timoc in U.S. Pat. No. 4,308,616 who adds a fault inserter to physical circuits.
Perhaps the conceptually simplest is the switch level. The switch-level representation of a circuit is an interconnection of transistors and the like. The type of transistor, whether bi-polar or MOS, depends upon the technology being used in the integrated circuit. Faults are fairly easily inserted into the switch level representation. However, once all the transistors are interconnected according to the design of the chip, there results a very complex, non-linear circuit. Such a switch level circuit is difficult to evaluate for the relation of inputs to outputs.
Another type of representation is a Boolean model in which Boolean gates, such as AND or OR gates, are used. A Boolean circuit is much easier to evaluate mathematically. The Boolean model may be more complex than the corresponding switch-level model, but once the model has been set up, sophisticated and efficient computer simulations are available.
Many bi-polar circuit elements can be readily converted to Boolean equivalents. However, MOS circuit elements are much more difficult to transform to a Boolean representation with the proper simulation of MOS faults.
One recently developed type of MOS circuit is a differential cascode voltage switch (DCVS). This type of circuit is disclosed by Heller et al in a technical article entitled "Cascode Voltage Switch Logic Family" appearing in Proceedings of IEEE International Solid-State Circuits Conference, Feb. 22-24, 1984, San Francisco, CA. This type of circuit is also described in patent application Ser. No. 554,146 filed Nov. 21, 1983 by W. R. Griffin et al. now U.S. Pat. No. 4,570,084 An example of a DCVS circuit is shown in FIG. 1. The circuit consists of any number of logic trees 10, each with an associated buffer and precharge circuit 11. The combination of a logic tree 10 and its buffer and precharge circuit 11 will be called a logic module. The buffer and precharge circuits 11 are generally identical but the internal structure of the logic trees 10 may be different. The DCVS circuit relies upon the presence of complementary signals at all points. Each primary input has a complement and true version PI0.sub.i and PI1.sub.i. The output of a logic module including the tree F.sub.i are complement and true versions F0.sub.i and F1.sub.i of the same logic signal. The inputs to the logic trees 10 are either the complementary versions of the primary inputs PI0.sub.I and PI1.sub.i or the complementary versions of the outputs F0.sub.i and F1.sub.i of different trees, collectively called major nets. The interconnections shown in FIG. 1 are purely for sake of example to demonstrate the variety available.
The details of the buffer and precharge circuit 11 are shown in FIG. 2 and its effect upon the logic tree 10 will now be described. The logic tree has a complement tree output T0 and a true tree output T1. Two upper precharge p-channel switches 12 and 14 separate the complement and true ouputs T0 and T1 from a positive voltage supply. A lower n-channel precharge switch 16 separates the grounding node R of the logic tree 10 from the ground. In a precharge period, the precharge signal controlling the precharge switches 12-16 goes low thus isolating the logic tree 10 from ground but connecting it to the positive power supply. Thus the two tree outputs T0 and T1 are charged.
The true tree output T1 is connected through a CMOS inverter of a p-channel switch 18 and a n-channel switch 20 to a true output node F1. The signal on the true output node F1 is fed back to the true tree output T1 through a p-channel feedback switch 22 connected to the positive voltage supply. The feedback switch 22 is a weak gate such that any substantial signal on the tree output T1 causes the feedback circuit to follow that signal. The feedback switch 22 compensates for leakage from the tree output T1 to ground and for signal fluctuations. Thus during the precharge period, the high signal on the precharged tree output T1 causes the true output node F1 to go low.
The complement tree output T0 has similar circuitry connecting it to a complement output node F0. In a normally functioning circuit, the signals on the tree outputs T0 and T1 are complementary to each other as are the output nodes F0 and F1. The CMOS inverters cause the output nodes F0 and F1 to be complementary to their corresponding tree outputs T0 and T1.
The logic tree 10 is implemented in NMOS, that is, with n-channel MOS switches. The logic tree 10 is controlled by major nets G0.sub.1, G1.sub.1, G0.sub.2 and G1.sub.2 of any even number. In normal operation, G0.sub.1 is complementary to G1.sub.1 and GO.sub.2 is complementary to G1.sub.2. As previously described, the major nets may be either primary inputs PI0.sub.i and PI1.sub.i to the DCVS circuit or may be connected to the output nodes F0 and F1 of a different logic tree.
The structure of the logic tree 10 depends on which logical function of its major net inputs it is designed to represent. An example of a logic tree is presented in FIG. 3. This logic tree 10 is seen to consists of three interconnected differential pairs 24 each controlled by complementary major nets G0.sub.i and G1.sub.i. This particular tree structure is chosen for sake of illustration only. The major nets to the different differential pairs 24 may be the same. The important thing is that, in a normal circuit for any signal value on a major net, one and only one switch in a differential pair 24 is conducting. Furthermore, as should become apparent by tracing paths from the grounding node R upward, for any combination of signals on major nets G0.sub.i and G1.sub.i there is one conducting path only either from the complement tree output T0 or from the true tree output T1 to the grounding node R. These facts are true in a faultless circuit for which the switches are properly operating and the major net G0.sub.i is complementary to the major net G1.sub.i.
Thus the fundamental building block of a logic tree 10 is the differential pair 24 shown in more detail in FIG. 4. The differential pair 24 consists of two n-channel switches 26 and 28, the gate electrodes of which are controlled by complementary major nets G0 and G1. The sources of both switches 26 and 28 are connected together to a common input source S. The drains of the two switches 26 and 28 are the output drains D0 and D1. In normal operation, regardless of the value of the signal on the major net G0, one of the two switches 26 and 28 is conducting and the other is non-conducting.
When the tree output nodes T0 and T1 have been properly precharged, once the lower precharge switch 16 is closed, either the tree output node T0 or the tree output node T1 is discharged, depending on the signal values of the major nets. This discharging is performed in what is called the evaluation phase. After evaluation, the signal on the tree output node T0 should be complementary to the signal on the node T1.
The rules for the interconnections of the differential pairs 24 are as follows. The major nets G0.sub.i and G1.sub.i are either primary inputs or are derived from the tree outputs T0 and T1 of other trees. These majors nets G0 and G1 have to be the true and complement forms of a single variable. The outputs D0 and D1 of a differential tree can only be connected to the input S of a single differential pair 24 at a higher level in the tree 10 or to a single tree output T0 or T1. The input S of a differential pair 24 can only be connected to the outputs D0 or D1 of one or more lower differential pairs in the tree 10 or to the grounding node R.
Also, the outputs D0 and D1 of different differential pairs 24 can be combined or dotted together. This dotting is used to share sub-trees and thus to reduce the number of differential pairs 24 to be perform the required logic function. It should be noted that the dotting at the tree outputs T0 and T1 and perhaps at other internal nodes results in a structure which is not strictly a tree, at least in the graph-theoretic sense.
During the precharge phase, because the tree outputs T0 and T1 are both held at the positive voltage supply, the output nodes F0 and F1 are both low or logic zero during the precharge. As a result, all the switches in the logic tree are non-conducting during the precharge.
DCVS circuits have many advantages. However, they suffer the previously described difficulty that they are composed of MOS switches and therefore are very difficult to stimulate as Boolean gates.